There is often a need to delay a pulse by some variable amount and in response to an electrical delay control signal which, perhaps, has been derived from a control loop of some kind. For example, there are memory system definitions where data read from a memory and an associated strobe signal, intended to instruct a receiving circuit to latch that data, are all generated with simultaneous leading edges. In such systems it is generally desirable to delay the strobe signal by a quarter cycle of the data transmission rate. This allows the data to settle and minor variations in arrival time for the various signals to be ignored. Various pulse delay circuits have been developed to perform this task. In a complex system such things as temperature change, power supply drift or shifts in other environmental variables can cause change either in the underlying data rate or in the amount of the delay circuit""s actual pulse delay produced by application of a given amount of delay control signal. (That is, the amount of delay needed or the amount provided, or both, might change.) In such complex systems it is common to cascade four generally identical adjustable delay elements connected to a common delay control signal, and then compare an undelayed instance of suitable clock signal with its fully delayed version using a coincidence detector, whose output servos the delay control signal. After some initial training this arrangement forms a control loop maintaining a one cycle delay produced by cascading four quarter cycle delays. The frequency of the clock signal is presumably also the underlying maximum repetition rate of the strobe signal. A delayed strobe signal having quarter cycle delay can then be obtained by applying the undelayed strobe signal to a separate fifth delay element controlled by the same common delay control signal. This arrangement has the advantage that the strobe is delayed by the right amount without requiring that it be synchronous with any other particular edge in the system.
It is conventional for the general nature of the delay element to be that of a voltage ramp compared to a comparison threshold. That is, an arriving edge is used to source or sink charge through a series RC (Resistance Capacitance) network formed of an input R and a grounded C. This forms at the junction of the R and C a voltage ramp whose output is applied to a subsequent switching element (typically a FET (Field Effect Transistor)) whose (fixed) switch point is the comparison threshold. The time constant of the RC network determines how much delay transpires before an applied arriving edge is replicated at the output. Prior art circuits have varied the RC time constant by switching in or out various amounts of component C that are in parallel when switched in and absent when switched out. The R is simply an appropriately sized FET. This works, but a disadvantage is that such capacitors consume valuable space within an IC (Integrated Circuit).
Furthermore, today""s low power IC""s often operate at low supply voltages, say at 2.5 to 3.5 volts. The FET threshold voltage (which is generally in the range of 0.5 to 0.7 volts) is a substantial fraction of that low supply voltage. Ordinarily, the maximum effective range of the ramp is the power supply voltage diminished by the threshold voltage. Threshold voltage is a function of how the FET""s are fabricated, and does not scale down as supply voltage is lowered to reduce power consumption. This limits the operating range of voltage ramps (the comparison threshold cannot be set within a FET threshold voltage of the supply voltage VDD), and reduces the range of delay that can be produced.
A solution to the problem of providing variable pulse delay in a voltage ramp/threshold circuit implemented on and IC is to vary the R instead of the C, which may be fixed. A variable R is formed by a plurality of FET""s arranged in parallel. The FET""s are sized according to a weighting scheme, which may be binary, and the amount of R produced is determined by which combination of FET""s is switched ON, rather than by analog variations in their drive level. If the plurality of sized parallel FET""s is made up of individual FET""s all of the same polarity, then the reduction in comparison range mentioned above will continue to obtain. That reduction in comparison range can be eliminated by replacing each such individual FET with a pair of similarly sized FET""s in parallel, the members of which pair are of opposite polarities. The additional FET""s have their own drive signals that correspond to the original drive signals.